M16CSLASH62P datasheet(21/87 Pages) RENESAS

21 / 87 page

M16C/62 Group (M16C/62P, M16C/62PT)

page 21

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB

comprise a register bank. There are two register banks.

Figure 2.1 Central Processing Unit Register

2.1 Data Registers (R0, R1, R2 and R3)

The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to

R3 are the same as R0.

The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.

R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-

bit data register (R2R0). R3R1 is the same as R2R0.

2.2 Address Registers (A0 and A1)

The register A0 consists of 16 bits, and is used for address register indirect addressing and address

A0.

In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).

Data registers (1)

Address registers (1)

Frame base registers (1)

Program counter

Interrupt table register

User stack pointer

Interrupt stack pointer

Static base register

Flag register

NOTES:

1. These registers comprise a register bank. There are two register banks.

R0H(R0's high bits)

b15

b8 b7

INTBH

USP

ISP

IPL

R0L(R0's low bits)

R1H(R1's high bits)R1L(R1's low bits)

b31

b19

INTBL

b15

b19

b15

FLG

b15

Reserved area

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved area

Processor interrupt priority level

The upper 4 bits of INTB are INTBH and

the lower 16 bits of INTB are INTBL.

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