M16CSLASH62P datasheet(43/87 Pages) RENESAS

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M16C/62 Group (M16C/62P, M16C/62PT)

5. Electrical Characteristics (M16C/62P)

page 43

Table 5.29 Memory Expansion and Microprocessor Modes

(for 2- to 3-wait setting, external area access and multiplex bus selection)

VCC1 = VCC2 = 5V

Switching Characteristics

(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)

th(BCLK-AD)

Address output hold time (refers to BCLK)

td(BCLK-CS)

Chip select output delay time

th(BCLK-CS)

Chip select output hold time (refers to BCLK)

th(RD-AD)

Address output hold time (refers to RD)

(Note 1)

td(BCLK-RD)

RD signal output delay time

th(BCLK-RD)

RD signal output hold time

th(WR-AD)

Address output hold time (refers to WR)

(Note 1)

td(BCLK-WR)

WR signal output delay time

td(BCLK-DB)

Data output delay time (refers to BCLK)

th(BCLK-DB)

Data output hold time (refers to BCLK)

td(DB-WR)

Data output delay time (refers to WR)

(Note 2)

th(BCLK-WR)

WR signal output hold time

th(RD-CS)

Chip select output hold time (refers to RD)

(Note 1)

th(WR-CS)

Chip select output hold time (refers to WR)

(Note 1)

th(WR-DB)

Data output hold time (refers to WR)

(Note 1)

1. Calculated according to the BCLK frequency as follows:

f(BCLK)

0.5 X 109

[ns]

2. Calculated according to the BCLK frequency as follows:

f(BCLK)

(n–0.5) X 109

–40

[ns]

3. Calculated according to the BCLK frequency as follows:

f(BCLK)

0.5 X 109

–25

[ns]

n is “2” for 2-wait setting, “3” for 3-wait setting.

td(BCLK-ALE)

ALE signal output delay time (refers to BCLK)

th(BCLK-ALE)

ALE signal output hold time (refers to BCLK)

– 4ns

th(ALE-AD)

ALE signal output hold time (refers to Adderss)

td(AD-RD)

RD signal output delay from the end of Adress

td(AD-WR)

WR signal output delay from the end of Adress

tdZ(RD-AD)

Address output floating start time

td(AD-ALE)

ALE signal output delay time (refers to Address)

(Note 3)

(Note 4)

–10

4. Calculated according to the BCLK frequency as follows:

f(BCLK)

0.5 X 109

[ns]

–15

NOTES:

HLDA output delay time

td(BCLK-HLDA)

See Figure 5.1

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