M16CSLASH62P datasheet(42/87 Pages) RENESAS

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M16C/62 Group (M16C/62P, M16C/62PT)

5. Electrical Characteristics (M16C/62P)

page 42

Table 5.28 Memory Expansion and Microprocessor Modes

(for 1- to 3-wait setting and external area access)

VCC1 = VCC2 = 5V

Switching Characteristics

(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)

Symbol

Standard

Measuring condition

Max.

Min.

ParameterUnit

td(BCLK-AD)

Address output delay time25ns

th(BCLK-AD)

Address output hold time (refers to BCLK)4

th(BCLK-CS)

Chip select output hold time (refers to BCLK)4

td(BCLK-ALE)

ALE signal output delay time15

th(BCLK-ALE)

ALE signal output hold time

–4

td(BCLK-RD)

RD signal output delay time25ns

th(BCLK-RD)

RD signal output hold time0

td(BCLK-WR)

WR signal output delay time

th(BCLK-WR)

WR signal output hold time

td(BCLK-DB)

Data output delay time (refers to BCLK)40ns

th(BCLK-DB)

Data output hold time (refers to BCLK)(3)

4ns

th(WR-DB)

Data output hold time (refers to WR)(3)

td(DB-WR)

Data output delay time (refers to WR)

1. Calculated according to the BCLK frequency as follows:

f(BCLK)

(n–0.5) X 109

– 40

[ns]

td(BCLK-CS)

Chip select output delay time25ns

th(RD-AD)

Address output hold time (refers to RD)0

th(WR-AD)

Address output hold time (refers to WR)

(Note 2)

3. This standard value shows the timing when the output is off,

and does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-up

(pull-down) resistance value.

Hold time of data bus is expressed in

t = –CR X ln (1 – VOL / VCC2)

by a circuit of the right figure.

For example, when VOL = 0.2VCC2, C = 30pF, R = 1k

Ω, hold time

of output “L” level is

t = – 30pF X 1k

Ω X ln (1 – 0.2VCC2 / VCC2)

= 6.7ns.

DBi

(Note 1)

(Note 2)

2. Calculated according to the BCLK frequency as follows:

f(BCLK)

0.5 X 109

[ns]

n is “1” for 1-wait setting, “2” for 2-wait

setting and “3” for 3-wait setting.

When n=1, f(BCLK) is 12.5MHz or less.

– 10

NOTES:

HLDA output delay time

40ns

td(BCLK-HLDA)

See Figure 5.1

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