CS5320 datasheet(92/160 Pages) AMCC

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S5320 – PCI Match Maker: PCI Bus Protocol

DS1656

AMCC Confidential and Proprietary

Revision 5.03 – June 14, 2006

Data Sheet

1. Memory Read Multiple and Memory Read Line are executed as a Memory Read.

2. Memory Write and Invalidate is executed as a Memory Write.

PCI BURST TRANSFERS

The PCI bus, by default, expects burst transfers to be

executed. To successfully perform a burst transfer,

both the initiator and target must order their burst

address sequence in an identical fashion. There are

two different ordering schemes: linear address incre-

menting and 80486 cache line fill sequencing.

The S5320 supports only linear burst ordering.

Attempts to perform burst transfers with a scheme

other than this will cause the STOP# signal to be

asserted during the first data phase, thus issuing a dis-

connect to the initiator. The S5320 completes the initial

data phase successfully, but asserting STOP# indi-

cates that the next access needs to be a completely

new cycle.

Some accesses to the S5320 controller do not support

burst transfers. For example, the S5320 does not

allow burst transfers when accesses are made to the

configuration or operation registers. Attempts to per-

form burst transfers to these regions will cause a

disconnect on the PCI bus, as described above.

Expansion ROM accesses also do not support bursts,

and will respond in the same way. Accesses to mem-

ory or I/O regions defined by the Base Address

Registers 1-4 may be bursts, if desired.

Table 41. PCI Bus Commands

C/BE[3:0]#

Command Type

Supported

0000

Interrupt Acknowledge

0001

Special Cycle

0010

I/O Read

Yes

0011

I/O Write

Yes

0100

Reserved

0101

Reserved

0110

Memory Read

Yes

0111

Memory Write

Yes

1000

Reserved

1001

Reserved

1010

Configuration Read

Yes

1011

Configuration Write

Yes

1100

Memory Read Multiple

Yes 1

1101

Reserved

1110

Memory Read Line

Yes 1

1111

Memory Write and Invalidate

Yes 2

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