CS5320 datasheet(27/160 Pages) AMCC

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S5320 – PCI Match Maker: PCI Configuration Registers

Revision 5.03 – June 14, 2006

AMCC Confidential and Proprietary

DS1656

Data Sheet

Each PCI bus device contains a unique 256-byte region called its configuration header space. Portions of this con-

figuration header are mandatory in order for a PCI agent to be in full compliance with the PCI specification. This

section describes each of the configuration space fields—its address, default values, initialization options, and bit

definitions—and also provides an explanation of its intended usage.

1. BADR 5 is not implemented in the S5320.

Table 10. Configuration Registers

Address Offset

Abbreviation

00h–01h

VID

Vendor Identification Register

02h–03h

DID

Device Identification Register

04h–05h

PCICMD

Command Register

06h–07h

PCISTS

Status Register

8h0

RID

Revision Identification Register

09h–0Bh

CLCD

Class Code Register

0Ch

CALN

Cache Line Size Register

0Dh

LAT

Latency Timer Register

0Eh

HDR

Header Type Register

0Fh

BIST

Built-in Self-test Register

10h–27h

BADR0-BADR5

Base Address Registers (0-5)1

28h–2Bh

–

Reserved

2Ch–2Dh

SVID

Subsystem Vendor Identification Register

2Eh–2Fh

SID

Subsystem Identification Register

30h–33h

XROM

Expansion ROM Base Address Register

34h–3Bh

–

Reserved

3Ch

INTLN

Interrupt Line Register

3Dh

INTPIN

Interrupt Pin Register

3Eh

MINGNT

Minimum Grant Register

3Fh

MAXLAT

Maximum Latency Register

40h–FFh

–

Not used

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