HC05RC16GRSSLASHD datasheet(63/122 Pages) NXP

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Core Timer

Core Timer Control and Status Register

MC68HC05RC16 — Rev. 3.0

General Release Specification

Core Timer

8.3 Core Timer Control and Status Register

The CTCSR contains the timer interrupt flag, the timer interrupt enable

bits, and the real-time interrupt rate select bits. Figure 8-2 shows the

value of each bit in the CTCSR when coming out of reset.

CTOF — Core Timer Overflow

CTOF is a read-only status bit set when the 8-bit ripple counter rolls

over from $FF to $00. Clearing the CTOF is done by writing a one to

TOFC. Writing to this bit has no effect. Reset clears CTOF.

RTIF — Real-Time Interrupt Flag

The real-time interrupt circuit consists of a 3-stage divider and a

one-of-four selector. The clock frequency that drives the RTI circuit is

E/212 (or E

÷ 4096 with three additional divider stages giving a

maximum interrupt period of 16 milliseconds at a bus rate of 2.024

MHz. RTIF is a clearable, read-only status bit and is set when the

output of the chosen (one-of-four selection) stage goes active.

Clearing the RTIF is done by writing a one to RTFC. Writing has no

effect on this bit. Reset clears RTIF.

TOFE — Timer Overflow Enable

When this bit is set, a CPU interrupt request is generated when the

CTOF bit is set. Reset clears this bit.

RTIE — Real-Time Interrupt Enable

When this bit is set, a CPU interrupt request is generated when the

RTIF bit is set. Reset clears this bit.

Address:

$08

Read:

CTOF

RTIF

TOFE

RTIE

RT1

RT0

Write:

TOFC

RTFC

Reset:

00000011

= Unimplemented

Figure 8-2. Core Timer Control and Status Register (CTCSR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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