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HC05RC16GRS/D bảng dữ liệu(PDF) 47 Page - NXP Semiconductors

tên linh kiện HC05RC16GRS/D
Giải thích chi tiết về linh kiện  General Release Specification
PDF  122 Pages
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nhà sản xuất  NXP [NXP Semiconductors]
Trang chủ  http://www.nxp.com
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Figure 5-2. Reset and POR Timing Diagram
PCH
PCL
OSC12
RESET5
INTERNAL
PROCESSOR
INTERNAL
ADDRESS
BUS1
3FFE
3FFF
V
DD
4064 t
CYC
t
CYC
t
RL
INTERNAL
DATA
BUS1
3FFE
3FFE
3FFE
3FFE
NEW PC
3FFF
NOTES:
1. Internal timing signal and bus information are not available externally.
2. OSC1 line is not meant to represent frequency. It is only used to represent time.
3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
4. VDD must fall to a level lower than VPOR to be recognized as a power-on reset.
5. The LPRST pin resets the CPU like RESET. However, 4064 POR cycles are executed first, before the reset vector address appears on the
internal address bus. (See 5.4 Low-Power External Reset (LPRST).)
3
NEW
NEW
OP
CODE
PCL
PCH
NEW PC
NEW PC
OP
CODE
NEW PC
CLOCK1
0 V
> VPOR 4
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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