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M66596FP bảng dữ liệu(PDF) 39 Page - Renesas Technology Corp |
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M66596FP bảng dữ liệu(HTML) 39 Page - Renesas Technology Corp |
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39 / 133 page ![]() M66596FP/WG rev .1.00 2006.3.14 page 37 of 127 BRDY interrupt status register [BRDYSTS] <Address: 46H> 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIPEBRDY ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 Bit Name Function S/W H/W Note 15-8 Nothing is placed here. These should be fixed at “0”. 7-0 PIPEBRDY BRDY interrupt status for theeach pipe 0: Interrupts are not issued. 1: Interrupts are issued. R/W(0) W(1) 3.2.3 *6) <<Note>> *6) The bit numbers correspond to the pipe numbers. Also, if factors are being generated for more than one pipe, an access cycle of at least 100 ns is required in order to clear the bits in succession, rather than simultaneously. NRDY interrupt status register [NRDYSTS] <Address: 48H> 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIPENRDY ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 Bit Name Function S/W H/W Note 15-8 Nothing is placed here. These should be fixed at “0”. 7-0 PIPENRDY NRDY interrupt for the each pipe 0: Interrupts are not issued. 1: Interrupts are issued. R/W(0) W(1) 3.2.4 *7) <<Note>> *7) The bit numbers correspond to the pipe numbers. Also, if factors are being generated for more than one pipe, an access cycle of at least 100 ns is required in order to clear the bits in succession, rather than simultaneously. BEMP interrupt status register [BEMPSTS] <Address: 4AH> 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIPEBEMP ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 Bit Name Function S/W H/W Note 15-8 Nothing is placed here. These should be fixed at “0”. 7-0 PIPEBEMP BEMP interrupt for the each pipe 0: Interrupts are not issued. 1: Interrupts are issued. R/W(0) W(1) 3.2.5 *8) <<Note>> *8) The bit numbers correspond to the pipe numbers. Also, if factors are being generated for more than one pipe, an access cycle of at least 100 ns is required in order to clear the bits in succession, rather than simultaneously. 2.9.1 Mirror bits of INTSTS0 registor and INTSTS1 SOFR , BEMP, NRDY, BRDY bit of INTSTS1 register are mirror bits of INTSTS0 register. When software reads, the same value as the same bit of INTSTS0 register can be read. When it writes, the same value as the same bit of INTSTS0 register is written in. |
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