PIC16F15213 datasheet(52/439 Pages) MICROCHIP

52 / 439 page

9.5.2

Overflow/Underflow Reset

If the STVREN bit is programmed to ‘1’, the device will be reset if the stack is PUSHed beyond the sixteenth level or

POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively).

9.6

Indirect Addressing

The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses

the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two

INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn

The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are

divided into three memory regions:

• Traditional/Banked Data Memory

• Linear Data Memory

• Program Flash Memory

Figure 9-19. Indirect Addressing

Filename:

Indirect Addressing.vsdx

Title:

Last Edit:

9/26/2019

First Used:

Notes:

Traditional

Data Memory

Linear Data

Memory

0x0000

0x1FFF

0x2000

0x2FEF

0x2FF0

Reserved

0x7FFF

0x8000

Program Flash

Memory

0xFFFF

PC value = 0x0000

PC value = 0x7FFF

FSR

Address

Range

9.6.1

Traditional/Banked Data Memory

The traditional or banked data memory is a region from FSR address 0x0000 to FSR address 0x1FFF. The

addresses correspond to the absolute addresses of all SFR, GPR and common registers.

PIC16F15213/14/23/24/43/44

Memory Organization

and its subsidiaries

Data Sheet

DS40002195E-page 52

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