UPSD3422EB40U6 datasheet(256/300 Pages) STMICROELECTRONICS

256 / 300 page

Obsolete

Product(s)

- Obsolete

Product(s)

Obsolete

Product(s)

- Obsolete

Product(s)

PSD module

UPSD3422, UPSD3433, UPSD3434, UPSD3454

256/300

Upon power-up, and while RST is asserted, the PSD module immediately loads its

configuration from non-volatile bits to configure the PLDs and other items. PLD logic is

operational and ready for use well before RST is de-asserted. The state of PLD outputs are

determined by equations specified in PSDsoft Express.

The Flash memories are reset to Read Array mode after any assertion of RST (even if a

program or erase operation is occurring).

Flash memory WRITE operations are automatically prevented while VDD is ramping up until

it rises above the VLKO voltage threshold at which time Flash memory WRITE operations

are allowed.

Once the UPSD34xx is up and running, any subsequent reset operation is referred to as a

warm reset, until power is turned off again. Some PSD module functions are reset in

different ways depending if the reset condition was caused from a power-up reset or a warm

reset. Table 203 on page 256 summarizes how PSD module functions are affected by

power-up and warm resets, as well as the affect of PSD module power-down mode (from

APD).

The I/O pins of PSD module Ports A, B, C, and D do not have weak internal pull-ups.

In MCU I/O mode, Latched Address Out mode, and Peripheral I/O mode, the pins of Ports

A, B, C, and D become standard CMOS inputs during a reset condition. If no external

devices are driving these pins during reset, then these inputs may float and draw excessive

current. If low power consumption is critical during reset, then these floating inputs should

be pulled up externally to VDD with a weak (100KΩ minimum) resistor.

In PLD I/O mode, pins of Ports A, B, C, and D may also float during reset if no external

device is driving them, and if there is no equation specified for the DPLD or GPLD to make

them an output. In this case, a weak external pull-up resistor (100K

Ω minimum) should be

used on floating pins to avoid excessive current draw.

The pins on Ports 1, 3, and 4 of the 8032 MCU module do have weak internal pull-ups and

the inputs will not float, so no external pull-ups are needed.

Table 203.

Function status during power-up reset, warm reset, power-down mode

Port configuration or

Power-up reset

Warm reset

APD Power-down mode

MCU I/O

Pins are in input mode

Pin logic state is unchanged

PLD I/O

Pin logic is valid after

internal PSD module

configuration bits are

loaded. Happens long

before RST is de-asserted

Pin logic is valid and is

determined by PLD logic

equations

Pin logic depends on inputs to

PLD (8032 addresses are

blocked from reaching PLD

inputs during power-down

mode)

Latched address out

mode

Pins are High Impedance

Pins are high impedance

Pins logic state not defined

since 8032 address signals

are blocked

Peripheral I/O mode

Pins are High Impedance

JTAG ISP and debug

JTAG channel is active

and available

JTAG channel is active

and available

JTAG channel is active and

available

PMMR0 and PMMR2

Cleared to 00h

Unchanged

Output of OMC Flip-flops

Cleared to ’0’

Depends on .re and .pr

equations

Depends on .re and .pr

equations

Obsolete

Product(s)

- Obsolete

Product(s)

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