UPSD3422EB40U6 datasheet(253/300 Pages) STMICROELECTRONICS

253 / 300 page

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UPSD3422, UPSD3433, UPSD3434, UPSD3454

PSD module

253/300

Figure 89.

Power-down mode flowchart

28.5.55

Chip select input (CSI)

Pin PD2 of Port D can optionally be configured in PSDsoft Express as the PSD module Chip

Select Input, CSI, which is an active-low logic input. By default, pin PD2 does not have the

CSI function.

When the CSI function is specified in PSDsoft Express, the CSI signal is automatically

included in DPLD chip select equations for FSx, CSBOOTx, RS0, and CSIOP. When the CSI

pin is driven to logic ’0’ from an external device, all of these memories will be available for

READ and WRITE operations. When CSI is driven to logic '1,' none of these memories are

available for selection, regardless of the address activity from the 8032, reducing power

consumption. The state of the PLD and port I/O pins are not changed when CSI goes to

logic ’1’ (disabled).

28.5.56

PLD non-turbo mode

The power consumption and speed of the PLDs are controlled by the Turbo Bit (Bit 3) in the

csiop PMMR0 register. By setting this bit to logic '1,' the Turbo mode is turned off and both

PLDs consume only standby current when ALL PLD inputs have no transitions for an

extended time (65 ns for 5 V devices, 100 ns for 3.3 V devices), significantly reducing

current consumption. The PLDs will latch their outputs and go to standby, drawing very little

current. When Turbo mode is off, PLD propagation delay time is increased as shown in the

AC specifications for the PSD module. Since this additional propagation delay also effects

the DPLD, the response time of the memories on the PSD module is also lengthened by that

same amount of time. If Turbo mode is off, the user should add an additional wait state to the

8032 BUSCON SFR register if the 8032 clock frequency is higher that a particular value.

Please refer to Table 51 on page 90 in the MCU module section.

Enable APD.

Set PMMR0,

Bit 1 = 1

RESET

OPTIONAL. Disable desired inputs to

PLDs by setting PMMR0 bits 4 and 5,

and PMMR2 bits 2 through 6

ALE idle

for 15 CLKIN

clocks?

PDN = 1, PSD

Module in Power-

Down Mode

YES

AI09183

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