UPSD3422EB40U6 datasheet(255/300 Pages) STMICROELECTRONICS

255 / 300 page

Obsolete

Product(s)

- Obsolete

Product(s)

Obsolete

Product(s)

- Obsolete

Product(s)

UPSD3422, UPSD3433, UPSD3434, UPSD3454

PSD module

255/300

28.5.60

PLD blocking bits

Blocking specific signals from entering the PLDs using bits of the csiop PMMR registers can

further reduce PLD AC current consumption by lowering the effective composite frequency

of inputs to the PLDs.

28.5.61

Blocking 8032 bus control signals

When the 8032 is active on the MCU module, four bus control signals (RD, WR, PSEN, and

ALE) are constantly transitioning to manage 8032 bus traffic. Each time one of these signals

has a transition from logic ’1’ to '0,' or 0 to '1,' it will wake up the PLDs if operating in non-

Turbo mode, or when in Turbo mode it will cause the affected PLD gates to draw current. If

equations in the DPLD or GPLD do not use the signals RD, WR, PSEN, or ALE then these

signals can be blocked which will reduce the AC current component substantially. These bus

control signals are rarely used in DPLD equations because they are routed in silicon directly

to the memory arrays of the PSD module, bypassing the PLDs. For example, it is NOT

necessary to qualify a memory chip select signal with an MCU write strobe, such as “fs0 =

address range & !WR_”. Only “fs0 = address range” is needed.

Each of the 8032 bus control signals may be blocked individually by writing to Bits 2, 3, 4,

and 5 of the PMMR2 register shown in Table 201 on page 249. Blocking any of these four

bus control signals only prevents them from reaching the PLDs, but they will always go to

the memories directly.

However, sometimes it is necessary to use these 8032 bus control signals in the GPLD

when creating interface signals to external I/O peripherals. But it is still possible to save

power by dynamically unblocking the bus signals before reading/writing the external device,

then blocking the signals after the communication is complete.

The user can also block an input signal coming from pin PC7 to the PLD input bus if desired

by writing to Bit 6 of PMMR2.

28.5.62

Blocking common clock, CLKIN

The input CLKIN (from pin PD1) can be blocked to reduce current consumption. CLKIN is

used as a common clock input to all OMC flip-flips, it is a general input to the PLD input bus,

and it is used to clock the APD counter. In PSDsoft Express, the function of pin PD1 must be

specified as “Common Clock Input, CLKIN” before programming the device with JTAG to get

the CLKIN function.

Bit 4 of PMMR0 can be set to logic ’1’ to block CLKIN from reaching the PLD input bus, but

CLKIN will still reach the APD counter.

Bit 5 of PMMR0 can be set to logic ’1’ to block CLKIN from reaching the OMC flip-flops only,

but CLKIN is still available to the PLD input bus and the APD counter.

See Table 200 on page 249 for details.

28.6

PSD module reset conditions

The PSD module receives a reset signal from the MCU module. This reset signal is referred

to as the “RST” input in PSD module documentation, and it is active-low when asserted. The

character of the RST signal generated from the MCU module is described in Section 19:

Supervisory functions on page 91.

Obsolete

Product(s)

- Obsolete

Product(s)

UPSD3422EB40U6 bảng dữ liệu(PDF) 255 Page - STMicroelectronics

UPSD3422EB40U6 bảng dữ liệu(HTML) 255 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL