UPSD3422EB40U6 datasheet(260/300 Pages) STMICROELECTRONICS

260 / 300 page

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PSD module

UPSD3422, UPSD3433, UPSD3434, UPSD3454

260/300

28.6.5

6-pin JTAG ISP (optional)

The optional signals TSTAT and TERR are programming status flags that can reduce

programming time by as much as 30% compared to 4-pin JTAG because this status

information does not have to be scanned out of the device serially. TSTAT and TERR must

be used as a pair for 6-pin JTAG operation.

●

TSTAT (pin PC3) indicates when programming of a single Flash location is complete.

Logic 1 = Ready, Logic 0 = busy.

●

TERR (pin PC4) indicates if there was a Flash programming error. Logic 1 = no error,

Logic 0 = error.

The pin functions for PC3 and PC4 must be selected as “Dedicated JTAG - TSTAT” and

“Dedicated JTAG - TERR” in PSDsoft Express to enable 6-pin JTAG ISP.

No 8032 firmware is needed to use 6-pin ISP because all ISP functions are controlled from

the external JTAG program/test equipment.

TSTAT and TERR are functional only when JTAG ISP operations are occurring, which

means they are non-functional during JTAG debugging of the 8032 on the MCU module.

Programming times vary depending on the number of locations to be programmed and the

JTAG programming equipment, but typical JTAG ISP programming times are 10 to 25

seconds using 6-pin JTAG. The signals TSTAT and TERR are not included in the IEEE

1149.1 specification.

Figure 92 on page 261 shows recommended connections on a circuit board to a JTAG

program/test tool using 6-pin JTAG. It is required to connect the RST output signal from the

JTAG program/test equipment to the RESET_IN input on the UPSD34xx. The RST signal is

driven by the equipment with an Open Drain driver, allowing other sources (like a push

button) to drive RESET_IN without conflict.

Note:

The recommended pull-up resistors and decoupling capacitor are illustrated in Figure 92.

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Product(s)

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