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UPSD3422EB40U6 bảng dữ liệu(PDF) 261 Page - STMicroelectronics |
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UPSD3422EB40U6 bảng dữ liệu(HTML) 261 Page - STMicroelectronics |
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261 / 300 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) UPSD3422, UPSD3433, UPSD3434, UPSD3454 PSD module 261/300 Figure 92. Recommended 6-pin JTAG connections 1. For 5 V UPSD34xx devices, pull-up resistors and VCC pin on the JTAG connector should be connected to 5 V system VDD. 2. For 3.3 V UPSD34xx devices, pull-up resistors and VCC pin on the JTAG connector should be connected to 3.3 V system VCC. 3. This signal is driven by an Open-Drain output in the JTAG equipment, allowing more than one source to activate RESET_IN. 28.6.6 Recommended JTAG connector There is no industry standard JTAG connector. STMicroelectronics recommends a specific JTAG connector and pinout for uPSD3xxx so programming and debug equipment will easily connect to the circuit board. The user does not have to use this connector if there is a different connection scheme. The recommended connector scheme can accept a standard 14-pin ribbon cable connector (2 rows of 7 pins on 0.1” centers, 0.025” square posts, standard keying) as shown in Figure 93. See the STMicroelectronics “FlashLINK, FL-101 User Manual” for more information. TMS - PC0 TCK - PC1 SRAM STBY or I/O - PC2 TSTAT - PC3 TERR - PC4 TDI - PC5 TDO - PC6 GENERAL I/O - PC7 JTAG CONN. 100k typical TMS TCK TDI TERR TSTAT TDO GENERAL I/O SIGNALS GND VCC (1,2) RST (3) uPSD34xx 0.01 µF CIRCUIT BOARD JTAG Programming or Test Equipment Connects Here 10k PUSH BUTTON or ANY OTHER RESET SOURCE DEBUG OPTIONAL TEST POINT 100k RESETIN AI10458 Obsolete Product(s) - Obsolete Product(s) |
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