SPC574S60 datasheet(39/77 Pages) STMICROELECTRONICS

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DS10601 Rev 6

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SPC574Sx

Electrical characteristics

The LV voltage is organized as one single domain. The LV can be generated internally (with

internal ballast) or externally, depending on a pin setting. The exposed pad is used to

connect the ground ring.

The ballasts are circuits placed in the padring, similarly as other pad circuits (supply or

input/output functions).

The S_BALLASTs are controlled by the digital regulator to source the static current. Total

current capability for the S_BALLAST on the LV domain is 325mA.

The D_BALLASTs are controlled by the linear regulator to source the dynamic current to

support the transient load response. Total current capability for all the D_BALLAST on the

LV domain is 100mA.

Transient time for the dynamic regulation is 20 µs for maximum 100mA on the LV.

The S_BALLASTs are enabled only in INTERNAL regulator mode (PWMODE = 1).

The D_BALLASTs are always enabled in INTERNAL regulator mode (PWMODE = 1).

The D_BALLASTs are enabled in EXTERNAL regulator mode (PWMODE = 0) only if the LV

supply is out of specs (+/- 5%) as tentative to avoid the device reset.

Figure 9. PMU concept scheme

Table 20. HV supply schemes

Internal

regulator

Number of HV

supplies

HV supply domains

Number of LV

supplies

Mandatory

ADC group #0

IO rail #0 + XOSC + PMU + Flash + IO rail #1

VDD_HV

VREF1

VREF2

FEEDBACK

VDD_LV

PMOS

NMOS

PMOS [14:0]

VDD_LV

VDD_HV

LEVEL SHIFTER

DIG REGULATOR

A/D

DIODE

VDD_HV

STATIC BALLAST (digital)

MIRROR

IREF

DYNAMIC BALLAST (linear)

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