Features
• AEC-Q100 qualified
• High performance e200z4d dual core
– 32-bit Power Architecture technology CPU
– Core frequency as high as 140 MHz
– Dual issue 5-stage pipeline in-order
execution core
– Variable Length Encoding (VLE)
– Core MPU
– Floating Point, End-to-End Error Correction
– 8 KB instruction cache with error detection
code
– 32 KB local data RAM and 4 KB data cache
along with 8 KB instruction cache
• 1600 KB (1.5 MB code + 64 KB data) on-chip
flash memory: supports read during program
and erase operations, and multiple blocks
allowing EEPROM emulation
• 128 KB on-chip RAM (96 KB on chip
RAM + 32 KB local data RAM)
• Multi-channel direct memory access controller
(eDMA) with 32 channels
• Comprehensive new generation ASILD safety
concept
– ASILD SEooC approach (Safety Element
out of Context)
– FCCU for collection and reaction to failure
notifications
– Memory Error Management Unit (MEMU)
for collection and reporting of error events
in memories
– End-to-end Error Correction Code
(e2eECC) logic
– Cyclic redundancy check (CRC) unit
• 8 enhanced 12-bit SAR analog converters
– 2 sets of: 3 ADCs and one supervisor ADC
– 1.5 μs conversion time at 12 MHz
– Up to 32 physical channels
– Dual Programmable CTU
• 4 general purpose eTimer units (6 channels
each)
• 4 FlexPWM units
– 2 (4 channels each) used for motor control
with hardware synchronization between the
control systems
– 2 (2 channels each) used for SWG
emulation
• Communication interfaces
– 4 LINFlexD modules
– 4 deserial serial peripheral interface (DSPI)
modules
– 2 MCAN interfaces with advanced shared
memory scheme (808 x 32-bit words for
MCAN0 and 520 x 32-bit words for
MCAN1) and CAN-FD support
– 1 FlexRay module with 2 channels, 128
message buffers
– 2 SENT interfaces (3 channels each)
• Dual phase-locked loops with stable clock
domain for peripherals and FM modulation
domain for computational shell
• Nexus Class 3 debug and trace interface
• On-chip CAN/UART Bootstrap loader with
BAF. Physical Interface (PHY) can be UART
• Advanced and flexible supply scheme
– On-chip voltage regulator for 1.2 V core
logic supply. Bypass mode supported for
external 1.2 V core logic supply
– 3.3 V or 5 V IO and ADC supply (2
independent power domains available)
• Junction temperature range -40 °C to 150 °C

Description
The SPC574Sx is a family of next generation microcontrollers built on the Power
Architecture embedded category.
The SPC574Sx family of 32-bit microcontrollers is the latest achievement in integrated
automotive application controllers. It belongs to an expanding family of automotive-focused
products designed to address the next wave of Chassis and Safety electronics applications
within the vehicle. The advanced and cost-efficient host processor core of this automotive
controller family complies with the Power Architecture embedded category and only
implements the VLE (variable-length encoding) APU, providing improved code density. It
operates at speeds of up to 140 MHz and offers high performance processing optimized for
low power consumption. It capitalizes on the available development infrastructure of current
Power Architecture devices and is supported with software drivers, operating systems and
configuration code to assist with users implementations.