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Electrical characteristics
SPC574Sx
60/77
DS10601 Rev 6
Figure 18. Nexus event trigger and test clock timings
15
—
CC D TDO propagation delay from falling edge of TCK(5)
—16
ns
16
—
CC D
TDO hold time with respect to TCK falling edge (minimum TDO
propagation delay)
2.25
—
ns
1.
Nexus timing specified at VDD_HV_IO_JTAG = 4.0 V to 5.5 V, and maximum loading per pad type as specified in the I/O
section of the data sheet.
2. tCYC is system clock period.
3. Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less
than the maximum functional capability of the design (system frequency / 4) depending on the actual peripheral frequency
being used. To ensure proper operation TCK frequency should be set to the peripheral frequency divided by a number
greater than or equal to that specified here.
4. This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the Absolute
minimum TCK period specification.
5. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
Table 39. Nexus debug port timing(1) (continued)
#
Symbol
C
Characteristic
Value
Unit
Min
Max
TCK
9
EVTI
EVTO



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