XIO2000 datasheet(109/150 Pages) TI

109 / 150 page

PCI Express Extended Configuration Space

November 2005

SCPS097B

5.12 Secondary Uncorrectable Error Severity Register

The uncorrectable error severity register controls the reporting of individual errors as ERR_FATAL or

ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When a bit is

cleared, the corresponding error condition is identified as nonfatal. See Table 5−10 for a complete description

of the register contents.

PCI Express extended register offset:

134h

Read-only, Read/Write

Default value:

0000 1340h

BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

Table 5−10. Secondary Uncorrectable Error Severity Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:14

RSVD

Reserved. Returns 00 0000 0000 0000 0000b when read.

13†

BRIDGE_ERROR_SEVR

Internal bridge error. This severity bit is associated with a PCI-X error and has no

effect on the bridge.

12†

SERR_DETECT_SEVR

SERR assertion detected

0 = Error condition is signaled using ERR_NONFATAL

1 = Error condition is signaled using ERR_FATAL (default)

11†

PERR_DETECT_SEVR

PERR assertion detected

0 = Error condition is signaled using ERR_NONFATAL (default)

1 = Error condition is signaled using ERR_FATAL

10†

DISCARD_TIMER_SEVR

Delayed transaction discard timer expired

0 = Error condition is signaled using ERR_NONFATAL (default)

1 = Error condition is signaled using ERR_FATAL

9†

UNCOR_ADDR_SEVR

Uncorrectable address error

0 = Error condition is signaled using ERR_NONFATAL

1 = Error condition is signaled using ERR_FATAL (default)

8†

ATTR_ERROR_SEVR

Uncorrectable attribute error. This severity bit is associated with a PCI-X error and has

no effect on the bridge.

7†

UNCOR_DATA_SEVR

Uncorrectable data error

0 = Error condition is signaled using ERR_NONFATAL (default)

1 = Error condition is signaled using ERR_FATAL

6†

SC_MSG_DATA_SEVR

Uncorrectable split completion message data error. This severity bit is associated with

a PCI-X error and has no effect on the bridge.

5†

SC_ERROR_SEVR

Unexpected split completion error. This severity bit is associated with a PCI-X error

and has no effect on the bridge.

RSVD

Reserved. Returns 0b when read.

3†

MASTER_ABORT_SEVR

Received master abort

0 = Error condition is signaled using ERR_NONFATAL (default)

1 = Error condition is signaled using ERR_FATAL

2†

TARGET_ABORT_SEVR

Received target abort

0 = Error condition is signaled using ERR_NONFATAL (default)

1 = Error condition is signaled using ERR_FATAL

1†

SC_MSTR_ABORT_SEVR

Master abort on split completion. This severity bit is associated with a PCI-X error and

has no effect on the bridge.

RSVD

Reserved. Returns 0b when read.

† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

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