XIO2000 datasheet(63/150 Pages) TI

63 / 150 page

Classic PCI Configuration Space

November 2005

SCPS097B

4.24 I/O Base Upper 16-Bit Register

This read/write register specifies the upper 16 bits of the I/O base register. See Table 4−15 for a complete

description of the register contents.

PCI register offset:

30h

Read/Write

Default value:

0000h

BIT NUMBER

RESET STATE

Table 4−15. I/O Base Upper 16-Bit Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:0

IOBASE

I/O base upper 16 bits. Defines the upper 16 bits of the lowest address of the I/O address range

that determines when to forward I/O transactions downstream. These bits correspond to address

bits [31:20] in the I/O address. The lower 20 bits are assumed to be 00000h.

4.25 I/O Limit Upper 16-Bit Register

This read/write register specifies the upper 16 bits of the I/O limit register. See Table 4−16 for a complete

description of the register contents.

PCI register offset:

32h

Read/Write

Default value:

0000h

BIT NUMBER

RESET STATE

Table 4−16. I/O Limit Upper 16-Bit Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:0

IOLIMIT

I/O limit upper 16 bits. Defines the upper 16 bits of the top address of the I/O address range that

determines when to forward I/O transactions downstream. These bits correspond to address

bits [31:20] in the I/O address. The lower 20 bits are assumed to be FFFFFh.

4.26 Capabilities Pointer Register

This read-only register provides a pointer into the PCI configuration header where the PCI power management

block resides. Since the PCI power management registers begin at 50h, this register is hardwired to 50h.

PCI register offset:

34h

Read-only

Default value:

50h

BIT NUMBER

RESET STATE

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