XIO2000 datasheet(45/150 Pages) TI

45 / 150 page

Feature/Protocol Descriptions

November 2005

SCPS097B

3.10.1

Serial-Bus Interface Implementation

To enable the serial-bus interface, a pullup resistor must be implemented on the SDA signal. At the rising edge

of PERST or GRST, whichever occurs later in time, the SDA terminal is checked for a pullup resistor. If one

is detected, then bit 3 (SBDETECT) in the serial-bus control and status register (see Section 4.58) is set.

Software may disable the serial-bus interface at any time by writing a 0b to the SBDETECT bit. If no external

EEPROM is required, then the serial-bus interface is permanently disabled by attaching a pulldown resistor

to the SDA signal.

The bridge implements a two-terminal serial interface with 1 clock signal (SCL) and 1 data signal (SDA). The

SCL signal is a unidirectional output from the bridge and the SDA signal is bidirectional. Both are open-drain

signals and require pullup resistors. The bridge is a bus master device and drives SCL at approximately

60 kHz during data transfers and places SCL in a high-impedance state (0 frequency) during bus idle states.

The serial EEPROM is a bus slave device and must acknowledge a slave address equal to A0h. Figure 3−14

illustrates an example application implementing the two-wire serial bus.

GPIO4 // SCL

GPIO5 // SDA

VDD_33

SCL

SDA

XIO2000

Serial

EEPROM

Figure 3−14. Serial EEPROM Application

3.10.2

Serial-Bus Interface Protocol

All data transfers are initiated by the serial-bus master. The beginning of a data transfer is indicated by a start

condition, which is signaled when the SDA line transitions to the low state while SCL is in the high state, as

illustrated in Figure 3−15. The end of a requested data transfer is indicated by a stop condition, which is

signaled by a low-to-high transition of SDA while SCL is in the high state, as shown in Figure 3−15. Data on

SDA must remain stable during the high state of the SCL signal, as changes on the SDA signal during the high

state of SCL are interpreted as control signals, that is, a start or stop condition.

XIO2000 bảng dữ liệu(PDF) 45 Page - Texas Instruments