CS47L85 datasheet(106/370 Pages) CIRRUS

106 / 370 page

CS47L85

106

Rev 4.3

SAMPLE RATE CONTROL

The CS47L85 supports multiple signal paths through the digital core. Stereo full-duplex sample rate conversion is provided

to allow digital audio to be routed between interfaces operating at different sample rates and/or referenced to asynchronous

clock domains.

Two independent clock domains are supported for the audio signal paths, referenced to SYSCLK and ASYNCCLK

respectively, as described in “Clocking and Sample Rates”. Every digital signal path must be synchronised either to SYSCLK

or to ASYNCCLK.

Up to five different sample rates may be in use at any time on the CS47L85. Three of these sample rates must be

synchronised to SYSCLK; the remaining two, where required, must be synchronised to ASYNCCLK.

Sample rate conversion is required when routing any audio path between digital functions that are asynchronous and/or

configured for different sample rates.

There are two Asynchronous Sample Rate Converters (ASRCs). Each ASRC supports 2-way stereo conversion paths

between the SYSCLK and ASYNCCLK domains. The ASRCs are described later, and is illustrated in Figure 38.

There are four Isochronous Sample Rate Converters (ISRCs). ISRC1 and ISRC2 support 2-way, 4-channel conversion

paths between sample rates on the SYSCLK domain, or between sample rates on the ASYNCCLK domain. ISRC3 and

ISRC4 provide similar functionality for up to 2 channels each. The ISRCs are described later, and are illustrated in Figure

39.

The sample rate of different blocks within the CS47L85 digital core are controlled as illustrated in Figure 37 - the *_RATE

registers select the applicable sample rate for each respective group of digital functions.

The *_RATE registers should not be changed if any of the *_SRCn registers associated with the respective functions is non-

zero. The associated *_SRCn registers should be cleared to 00h before writing new values to the *_RATE registers. A

minimum delay of 125us should be allowed between clearing the *_SRCn registers and writing to the associated *_RATE

registers. See Table 22 for further details.

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