71M6541DSLASHFSLASHG datasheet(100/166 Pages) MAXIM

100 / 166 page

71M6541D/F/G and 71M6542F/G Data Sheet

100

Rev 5

•

GAIN_ADJ2 provides compensation for the remotely connected IB shunt current sensor and compensates

for the 71M6x01 VREF. The designer may optionally add compensation for the shunt connected to the

71M6x01 into the PPMC and PPMC2 coefficients for this channel.

Table 73: GAIN_ADJn Compensation Channels

Gain Adjustment Output

CE RAM Address

71M6541D/F/G

71M6542F/G

GAIN_ADJ0

0x40

VA, VB

GAIN_ADJ1

0x41

GAIN_ADJ2

0x42

In the demonstration code, temperature compensation behavior is determined by the values stored in the

PPMC and PPMC2 coefficients, which are setup by the MPU demo code at initialization time from values

that are previously stored in EEPROM.

To disable temperature compensation in the demonstration code, PPMC and PPMC2 are both set to zero

for each of the three GAIN_ADJn channels. To enable temperature compensation, the PPMC and PPMC2

coefficients are set with values that match the expected temperature variation of the corresponding

channel.

For VREF compensation, both the linear coefficient PPMC and the quadratic coefficient PPMC2, are

determined for the 71M654x as described in 4.7.2 Temperature Coefficients for the 71M654x. For

information on determining the PPMC and PPMC2 coefficients for the 71M6x01 VREF, refer to the

71M6xxx Data Sheet.

The compensation for the external error sources is accomplished by summing the PPMC value

associated with VREF with the PPMC value associated with the external error source to obtain the final

PPMC value for the sensor channel. Similarly, the PPMC2 value associated with VREF is summed with

the PPMC2 value associated with the external error source.

To determine the contribution of the current shunt sensor to the PPMC and PPMC2 coefficients, the

designer must either know the temperature coefficients of the shunt from its data sheet or obtain it by

laboratory measurement. The designer must consider component variation across mass production to

ensure that the product will meet its accuracy requirement across production.

4.8

Connecting I

2C EEPROMs

2C EEPROMs or other I2C compatible devices should be connected to the DIO pins SEGDIO2 and

SEGDIO3, as shown in Figure 39.

Pull-up resistors of roughly 10 k

Ω to V3P3D (to ensure operation in BRN mode) should be used for both

SDCK and SDATA signals. The DIO_EEX[1:0] (I/O RAM 0x2456[7:6]) field in I/O RAM must be set to 01

in order to convert the DIO pins SEGDIO2 and SEGDIO3 to I

2C pins SDCK and SDATA.

Figure 39: I

2C EEPROM Connection

SEGDIO2/SDCK

EEPROM

SDCK

SDATA

V3P3D

10 k

71M654x

SEGDIO3/SDATA

71M6541D/F/G bảng dữ liệu(PDF) 100 Page - Maxim Integrated Products

71M6541D/F/G bảng dữ liệu(HTML) 100 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL