SPC572L64F2 datasheet(81/112 Pages) STMICROELECTRONICS

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SPC572Lx

Electrical characteristics

111

9tSUO

D SOUT data valid

time from SCK

CPHA = 0(10)

SOUT and SCK drive strength

Very strong

25 pF

—

7.0 + tSYS(5) ns

Strong

50 pF

—

9.0 + tSYS(5)

Medium

50 pF

—

25.0 + tSYS(

SOUT data valid

time from SCK

CPHA = 1(10)

SOUT and SCK drive strength

Very strong

25 pF

—

7.0

Strong

50 pF

—

9.0

Medium

50 pF

—

25.0

SOUT data hold time (after SCK edge)

tHO

D SOUT data hold

time after SCK

CPHA = 0(11)

SOUT and SCK drive strength

Very strong

25 pF

–7.7 + tSYS(5)

—ns

Strong

50 pF

–11.0 + tSYS(5)

—

Medium

50 pF

–15.0 + tSYS(5)

—

SOUT data hold

time after SCK

CPHA = 1(11)

SOUT and SCK drive strength

Very strong

25 pF

–7.7

—

Strong

50 pF

–11.0

—

Medium

50 pF

–15.0

—

1. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

2. All timing values for output signals in this table are measured to 50% of the output voltage.

3. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may

cause incorrect operation.

4. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable

using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous

SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same

edge of DSPI_CLKn).

5. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 80 MHz (min

tSYS =10 ns).

6. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable

using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK

clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge

of DSPI_CLKn).

7. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide

ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

8. PCSx and PCSS using same pad configuration.

9. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds.

10. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using

DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set to

11. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same

value.

Table 42. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0

or 1(1) (continued)

Symbol

Characteristic

Condition

Value(2)

Unit

Pad drive(3)

Load (CL)Min

Max

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