SPC572L64F2 datasheet(56/112 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC572Lx

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DocID027866 Rev 5

tSETTLING

D Settling time after

mux change

Analog inputs are muxed

HPF = ON

——

δGROUP +

3*fADCD_S

—

HPF = OFF

—

δGROUP +

2*fADCD_S

—

tODRECOVERY CC

D Overdrive recovery

time

After input comes within

range from saturation

HPF = ON

——

δGROUP +

fADCD_S

—

HPF = OFF

—

δGROUP

—

CS_D

D S/D ADC sampling

capacitance after

sampling switch(14)

GAIN = 1, 2, 4, 8

—

75*GAIN

GAIN = 16

—

600

IBIAS

D Bias consumption

At least 1 ADCD enabled

—

3.5

IADV_D

P VDD_HV_ADV power

supply current

(single S/D ADC)

S/D ADC Dynamic

consumption

——

3.5

IADCS/D_REFH CC

T S/D ADC Reference

High Current

Dynamic consumption

(Conversion)

——

3.5

µA

Static consumption (Power

down)

——

1. Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings

only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device

reliability or cause permanent damage to the device.

2. For input voltage above the maximum and below the clamp voltage of the input pad, there is no latch-up concern, and the

signal will only be ‘clipped’.

3. VINP is the input voltage applied to the positive terminal of the SDADC.

4. VINM is the input voltage applied to the negative terminal of the SDADC.

5. Maximum input of 166.67 kHz supported with reduced accuracy. See SNR specifications.

6. When using a GAIN setting of 16, the conversion result will always have a value of zero in the least significant bit. This

gives an effective resolution of 15 bits.

7. Offset and gain error due to temperature drift can occur in either direction (+/-) for each of the SDADCs on the device.

8. Calibration of gain is possible when gain = 1.

Offset Calibration should be done with respect to 0.5*VDD_HV_ADR for differential mode and single ended mode with

negative input=0.5*VDD_HV_ADR.

Offset Calibration should be done with respect to 0 for "single ended mode with negative input=0".

Both offset and Gain Calibration is guaranteed for ±5% variation of VDD_HV_ADR, ±10% variation of VDD_HV_ADV, and ± 50

°C temperature variation.

9. Conversion offset error must be divided by the applied gain factor (1, 2, 4, 8, or 16) to obtain the actual input referred offset

error.

10. This parameter is guaranteed by bench validation with a small sample of typical devices, and tested in production to a

value of 6 dB less.

11. Impedance given at fADCD_M = 16 MHz. Impedance is inversely proportional to frequency:

ZDIFF(fADCD_M)=16 MHz/fADCD_M * ZDIFF

ZCM(fADCD_M) =16MHz/fADCD_M * ZCM

12. SNR values guaranteed only if external noise on the ADC input pin is attenuated by the required SNR value in the

frequency range of fADCD_M – fADCD_S to fADCD_M + fADCD_S, where fADCD_M is the input sampling frequency, and fADCD_S

is the output sample frequency. A proper external input filter should be used to remove any interfering signals in this

frequency range.

13. The ±1% passband ripple specification is equivalent to 20 * log10 (0.99) = 0.087 dB.

Table 26. SDn ADC electrical specification(1) (continued)

Symbol

Parameter

Conditions

Value

Unit

Min

Typ

Max

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