AD4134 datasheet(72/92 Pages) AD

72 / 92 page

Data Sheet

AD4134

DIAGNOSTICS

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Rev. 0 | 72 of 92

The device checks the input ODR signal frequency after the PLL

locks and sets the ERR_ASRC bit if the ODR frequency detected

is outside the range for the particular type of filter selected as

specified in Table 19. This bit is cleared on a read.

For example, if the ODR input is set to 600 kSPS and the type of

filter set is wideband, this error is flagged. There is no data output in

this scenario.

DIGITAL FILTER OVERFLOW AND

UNDERFLOW

The digital filter overflow/underflow occurs when the input is over-

range or due to an incorrect setting of the gain and calibration

corresponding channel bit in the DIG_FILTER_OFUF register when

an overflow or underflow condition is detected.

For proper usage of this diagnostic feature, it is recommended to

read back these flags after power-up.

DCLK ERROR

The device has a built-in feature to flag insufficient numbers of data

clocks needed to clock out the complete frame.

The user must program or provide a data clock that is fast enough

to clock out the complete frame for the given ODR and ensure that

for the gated mode,

ODR Time > tDCLK × Frame Size + 6 × tDCLK or tDIGCLK (whichever

is higher)

And for free mode,

ODR Time > tDCLK × Frame Size + 4 × tDCLK or tDIGCLK (whichever

is higher)

The ERR_DCLK flag sets if the programmed or provided DCLK

frequency is such that Equation 1 is not met, resulting in an

insufficient number of data clocks to clock out the entire frame. This

bit is cleared on a read.

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