AD4134 datasheet(69/92 Pages) AD

69 / 92 page

Data Sheet

AD4134

DIGITAL INTERFACE

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Rev. 0 | 69 of 92

Figure 121. Data Interface Timing Example of a Device with Different ODR Settings on Each Channel

Digital Interface Reset

Bit 1 of the INTERFACE_CONFIG_B register (DIG_IF_RESET)

resets the data interface. In multidevice configuration, this bit syn-

chronizes data channel outputs to achieve device to device channel

phase matching. This bit is self clearing and only available for use

in SPI slave mode operation. Refer to the Multidevice Synchroniza-

tion section.

MINIMUM I/O MODE

Certain applications require a minimum number of I/O lines to be

used for interfacing with the AD4134. This requirement may be due

to the limited number of I/Os available on the digital host, or for

cost reasons, to minimize the number of digital isolation channels

required in an isolated application.

The AD4134 is designed to support both register and data access

using as few as only four unidirectional I/O lines.

The minimum I/O mode configuration essentially combines the

digital host to interface with the AD4134 with only one SPI port as

master.

The trade-off of minimizing the number of I/O ports is more compli-

cated firmware design and a potentially higher CPU processing

load.

On power-on, the AD4134 boots up in minimum I/O mode and

a toggle on pin makes the device exit the minimum I/O mode.

Also, SPI CRC is enabled in minimum I/O mode and cannot be

disabled. All SPI packets must be 24 bits, which is R/W + Address

(8-bit), data (8-bit), and CRC (8-bit), as described in Figure 114.

To configure the AD4134 to operate with a minimum number of IO

lines, perform the following sequence:

1. Connect the FORMAT0/ pin to ground.

2. Externally connect DCLK to the FORMAT1/SCLK pin.

3. Configure DCLK to be a gated input.

4. Set ASRC slave mode.

5. Set FORMATx to 00 wherein data from all four ADC channels

are converged and output through DOUT0.

6. Set the SDO_PIN_SRC_SEL bit to 1.

Figure 122. Signal Connection Diagram of Minimum I/O Configuration

In minimum I/O mode, the user can use the DEC3/SDO pin for both

the SDO and DOUT0 outputs are allowed to be enabled at any

given time. Setting the SDO_PIN_SRC_SEL bit to 1 causes the

signal on DOUT0 to be duplicated on the DEC3/SDO pin.

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