AD4134 datasheet(44/92 Pages) AD

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Data Sheet

AD4134

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The AD4134 offers users a multichannel platform measurement

solution for ac and dc signal processing. Flexible filtering allows

the AD4134 to be configured to simultaneously sample ac and

dc signals on a per channel basis. The ASRC allows users to

granularly set the output data rate controlling the input bandwidth

of the measurement. This ability, coupled with the flexibility of

the digital filter, allows the user to choose the right application

settings and meet latency, bandwidth, and performance targets.

Key capabilities that allow users to choose the AD4134 as their

platform high resolution ADC are highlighted as follows:

►

Four fully differential analog inputs

►

Fast throughput simultaneous sampling ADCs catering for input

signals up to 391.5 kHz

►

Two selectable power modes (high performance and low power)

for scaling the current consumption and input bandwidth of the

ADC to achieve optimal measurement efficiency

►

Wideband, low ripple, digital filter for ac measurement

►

Fast sinc3 filter for precision low frequency, low latency measure-

ment

►

Two ASRC modes (master mode and slave mode) allow user

flexibility in digital interface

►

Two antialias modes enabling the user to choose higher levels of

alias rejection

►

Choice of SPI or pin strapped configuration option

►

Offset, gain, and phase calibration registers per channel

►

Common-mode voltage output buffer to set the common-mode

voltage of the input

►

On-board 1.8 V LDO regulators for single-supply operation

Refer to Figure 87 and Table 20 for the typical connections and

minimum requirements to start using the AD4134.

Figure 87. Typical Connections Diagram

Table 20. Requirements to Operate the AD4134

Requirement

Description

Power Supplies

5 V AVDD5 and DVDD5 supply, 1.8 V − IOVDD, CLKVDD, AVDD1V8, and DVDD1V8 (LT8606, LT8607)

External Reference

4.096 V or 5 V (ADR444/ADR445)

Input Stage

AD8421, ADA4075-2, ADA4945-1, LTC6363, LTC6373

External Clock

Crystal or a CMOS/LVDS clock for the ADC modulator sampling

Field Programmable Gate Array (FPGA)

or Digital Signal Processor (DSP)

1.65 V to 1.95 V digital I/O level

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