AD4134 datasheet(68/92 Pages) AD

68 / 92 page

Data Sheet

AD4134

DIGITAL INTERFACE

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Rev. 0 | 68 of 92

Frame Length Examples

In Case 1, the following conditions apply:

►

16-bit output format

►

No status or CRC header

►

Parallel output on all four DOUTx pins

►

No daisy chain

►

Averaging disabled

The output data frame length is 16/8 = 2 bytes per ODR period on

each of the four DOUTx pins.

In Case 2, the following conditions apply:

►

24-bit data format

►

Status and CRC header enabled

►

Output on two DOUTx pins

►

Daisy chain three devices

►

Averaging disabled

The output data frame length is (24/8 + 1) × 2 × 3 = 24 bytes per

ODR period on each of the two DOUTx pins.

In Case 3, the following conditions apply:

►

24-bit output format

►

Status/CRC header enabled

►

Output on one DOUTx pins

►

Daisy-chain two devices

►

4:1 averaging

The output data frame length is (24/8 + 1) × 4 × 2/4 = 8 bytes per

ODR period.

DCLK Frequency Selection

The user must ensure an adequate DCLK frequency is used to

clock out the full length of the data frame in time.

The maximum supported DCLK frequency on the AD4134 is 48

MHz as an output and 50 MHz as an input.

Gated DCLK Output Cycles

When DCLK is configured as a gated output, the AD4134 uses an

internal counter to control the number of DCLK cycles to output

after each ODR pulse. The device automatically adjusts the number

of DCLK cycles to output according to its data frame and format

configuration.

However, in daisy-chain mode, the device has no inherent knowl-

edge of the number of devices connected on the chain.

In pin control mode, unless the device is configured to operate

in quad channel parallel output mode, it assumes a daisy-chain

configuration. If the DCLK pin is configured as a gated output,

the device assumes that four devices are on the daisy chain. The

number of DCLK cycles it generates after each ODR pulse is equal

to four times the data frame length of the devices.

In SPI control mode, the user has the flexibility to program

the number of devices on the daisy chain through the DAISY_

CHAIN_DEV_NUM bits. The value acts as a multiplier to the num-

ber of DCLK cycles the device outputs after each ODR pulse when

the DCLK is configured as a gated output.

Gated DCLK Output Cycles Examples

In Case 1, the following conditions apply:

►

16-bit output format

►

No status or CRC header

►

Single-channel daisy-chain mode

►

Pin control mode operation

►

DCLK configured as gated output

The device outputs 16 × 4 = 64 DCLK cycles after each ODR pulse.

In Case 2, the following conditions apply:

►

24-bit output format

►

Status and CRC header enabled

►

Dual-channel daisy-chain mode

►

Averaging disabled

►

SPI control mode operation

►

DAISY_CHAIN_DEV_NUM = 3 (decimal)

The device outputs (24 + 8) × 2 × 3 = 192 DCLK cycles after each

ODR pulse.

Channel Dependent ODR

In SPI control mode, the AD4134 supports the configuration of dif-

ferent ODR rates on each channel using the CHANNEL_ODR_SE-

LECT register. The rate must be a power of two fraction of the

signal frequency on the ODR pin and is limited to a minimum of 1/8

of the main ODR frequency.

Each channel updates its conversion output based on the ODR rate

of the channel. For example, if a channel is configured to have an

output data rate of ODR/4, its output data updates once every four

ODR cycles. Figure 121 shows an example of the data interface

timing of a device with different output data rate settings on each

channel.

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