MPC8560CPX667JC datasheet(25/108 Pages) NXP

25 / 108 page

MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2

Freescale Semiconductor

Ethernet: Three-Speed, MII Management

Figure 7 shows the GMII transmit AC timing diagram.

Figure 7. GMII Transmit AC Timing Diagram

7.2.1.2

GMII Receive AC Timing Specifications

Table 22 provides the GMII receive AC timing specifications.

GTX_CLK data clock rise and fall time

tGTXR, tGTXF

2,4

——

1.0

Notes:

1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV

symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative

to the time date input signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII

transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date

input signals (D) going invalid (X) or hold time. Note that, in general, the clock reference symbol representation is

based on three letters representing the clock of a particular functional. For example, the subscript of tGTX represents

the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R

(rise) or F (fall).

2.Signal timings are measured at 0.7 V and 1.9 V voltage levels.

3.Guaranteed by characterization.

4.Guaranteed by design.

Table 22. GMII Receive AC Timing Specifications

At recommended operating conditions with LVDD of 3.3 V ± 5%, or LVDD=2.5V ± 5%.

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

RX_CLK clock period

tGRX

—8.0

—

RX_CLK duty cycle

tGRXH/tGRX

—

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK

tGRDVKH

2.0

—

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK

tGRDXKH

0.5

—

Table 21. GMII Transmit AC Timing Specifications (continued)

At recommended operating conditions with LVDD of 3.3 V ± 5%, or LVDD=2.5V ± 5%.

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

GTX_CLK

TXD[7:0]

tGTKHDX

tGTX

tGTXH

tGTXR

tGTXF

tGTKHDV

TX_EN

TX_ER

MPC8560CPX667JC bảng dữ liệu(PDF) 25 Page - NXP Semiconductors

MPC8560CPX667JC bảng dữ liệu(HTML) 25 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL