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DA9072 bảng dữ liệu(PDF) 31 Page - Dialog Semiconductor |
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DA9072 bảng dữ liệu(HTML) 31 Page - Dialog Semiconductor |
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31 / 113 page ![]() DA9072 Ultra-Low Quiescent Current PMIC Datasheet Revision 3.0 14-Jun-2021 CFR0011-120-00 31 of 113 © 2021 Dialog Semiconductor Table 22: Battery Thermal Protection Measures Temperature Range Voltage at TEMP_SNS Charger Action Interrupt name TBAT < TLO VTEMP_SNS > VTEMP_LOR Charging terminated TS COLD TCOLD < TBAT < TCOOL VTEMP_LO > VTEMP_SNS > VTEMP_COOL Charge current = 0.5 * ICHG setting TS COOL TCOOL < TBAT < TWARM VTEMP_COOL > VTEMP_SNS > VTEMP_WARM Normal charging TWARM < TBAT < THI VTEMP_WARM > VTEMP_SNS > VTEMP_HI Target voltage (VBAT_CHG) reduced by 140 mV TS WARM THI < TBAT VTEMP_SNS < VTEMP_HI Charging terminated TS HOT VTEMP_SNS > VOFF_TEMP_SNS Temp sense disabled, Optional Fault TS OFF Setting the Resistor Divider The four temperature thresholds are fixed percentages of VTEMP, see Section 2.4.2. VTEMP is enabled in short pulses to allow the battery temperature to be monitored without drawing unnecessary current through the resistor divider. VTEMP is derived from the VDD_SYS voltage. The TEMP_SNS voltage is measured after a deglitch time of 10 msec, which precludes any need for filtering at TEMP_SNS. To avoid measurement error, no filter capacitance larger than 10 nF should be added to TEMP_SNS pin. Temperature monitoring can be disabled by TS_EN_CHG (register 0x0026 [0]) and TS_EN_DISCHG bits (register 0x0026 [1]), or by pulling TEMP_SNS above the VOFF_TEMP_SNS threshold (TS_OFF state). The TS_OFF state disables temperature sensing and can optionally be flagged as a fault condition by setting register bit TS_OFF_MODE (register 0x0026:[2]) = 0x1. When TEMP_SNS is pulled high to enter TS_OFF state, the state is latched until TEMP_SNS is disabled. Temp sense is disabled in Hi-Z mode. Each temp sense threshold generates an interrupt at SYS_FLT and each has an event bit at register SYS_ISR_1 (0x0004 [7:4]) and SYS_ISR_2 (0x0005 [6]). The battery NTC interfaces to the TEMP_SNS input through a resistive divider, see Figure 21. TEMP_SNS RHI VTEMP RLO VBAT NTC Figure 21: Battery Temperature Sensing with NTC The resistor divider values (RHI and RLO) are selected as shown below so that the cold and hot TEMP_SNS thresholds are reached at the corresponding NTC values. |
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