DA9072 datasheet(28/113 Pages) DIALOG

28 / 113 page

DA9072

Ultra-Low Quiescent Current PMIC

Datasheet

Revision 3.0

14-Jun-2021

CFR0011-120-00

28 of 113

Functional Description

4.1

Overview

In a typical application, DA9072 manages two power inputs: a battery at pin VBAT and a USB supply

at pin VDD_PWR. The larger of these supplies feeds the unregulated system output voltage at pin

VDD_SYS. VDD_SYS in turn is used as the input supply to the linear charger, buck, and LDOs. Due

to its extremely low IQ (< 1 µA), the buck can remain always on as the primary system power rail

without draining the battery excessively.

When USB power is present, VDD_SYS is near 5 V and the linear charger is active. When USB

power in not connected, VDD_SYS tracks the battery voltage. DA9072 actively manages this power

path, reducing charging current and input current as necessary, and allowing VDD_SYS to draw

current from both supplies during peak loads.

The DA9072 includes multiple configurable protection features including battery and input over-

current. All settings can be controlled by I2C, but stand-alone operation is also possible with features

such as a pushbutton input timer, resistor programmable charge settings, and the MODE pin to

enable and disable charging.

As there are two input sources, DA9072 has multiple regions of operation, see Figure 20.

VDD_PWR

VBAT

5.5 V

VDD_PWR

UVLO (3.4 V)

VBAT_UVLO

(2.0 V to 3.0 V)

POR

4.65 V

20 V

OVP

SLEEP

ACTIVE POWER / CHARGING

ACTIVE BATTERY,

HiZ, or SHIP

UVLO

Figure 20: Regions of Operation

DA9072 bảng dữ liệu(PDF) 28 Page - Dialog Semiconductor