AT25SL641 datasheet(34/76 Pages) DIALOG

tên linh kiện	AT25SL641

Giải thích chi tiết về linh kiện	64-Mbit, 1.7V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

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AT25SL641

DS-25SL641–113F–12/2018

7.17

4 KByte Block Erase (20h)

The Block Erase instruction is used to erase the data of the selected block by setting the memory locations to “1”. The

instruction is used to erase a 4 KB block. Prior to the Block Erase Instruction, the Write Enable instruction must be

issued. The instruction is initiated by driving the CS pin low and shifting the instruction code 20h followed by a 24-bit

block address (A23 - A0). (Please refer to Figure 7-25 and Figure 7-26).

The CS pin must go high after the eighth bit of the last byte has been latched in, otherwise, the Block Erase instruction

will not be executed. After CS goes high, the self-timed Block Erase instruction commences for a time duration of t

(See AC Characteristics).

While the Block Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the

status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished

and the device is ready to accept other instructions. When the BUSY bit is asserted, the Write Enable Latch (WEL) bit in

the Status Register is cleared to 0.

Figure 7-25. 4 KByte Block Erase Instruction (SPI Mode)

Figure 7-26. 4 KByte Block Erase Instruction (QPI Mode)

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