AT25SL641 datasheet(23/76 Pages) DIALOG

tên linh kiện	AT25SL641

Giải thích chi tiết về linh kiện	64-Mbit, 1.7V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

PDF	76 Pages

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AT25SL641

DS-25SL641–113F–12/2018

Figure 7-8.

Write Status Register-2 Instruction (SPI Mode)

Figure 7-9.

Write Status Register-2 Instruction (QPI Mode)

7.8

Set Read Parameters (C0h)

In QPI mode, to accommodate a wide range of applications with different needs for either maximum read frequency or

minimum data access latency, t h e Set Read Parameters (C0h) instruction can be used to configure the number of

dummy clocks for the Fast Read (0Bh), Fast Read Quad I/O (EBh), and Burst Read with Wrap (0Ch) instructions, and

to configure the number of bytes of wrap length for the Burst Read with Wrap (0Ch) instruction.

In Standard SPI mode, the Set Read Parameters (C0h) instruction is not accepted. The dummy clocks for various Fast

Read instructions in Standard/Dual/Quad SPI mode are fixed. The wrap length is set by the W6-W5 bits in the Set Burst

with Wrap (77h) instruction. This setting remains unchanged when the device is switched from Standard SPI mode to

QPI mode.

The default wrap length after a power up or a Reset instruction is 8 bytes, and the default number of dummy clocks is 4.

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