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AT25SL641

DS-25SL641–113F–12/2018

Quad Input/ Output Data

IO0 = (D4, D0S)

IO1 = (D5, D1S)

IO2 = (D6, D2S)

IO3 = (D7, D3S)

Fast Read Quad I/O Data Output

IO0 = (x, x, x, x, D4, D0S)

IO1 = (x, x, x, x, D5, D1S)

IO2 = (x, x, x, x, D6, D2S)

IO3 = (x, x, x, x, D7, D3S)

10.

SC = security register

11.

The M7-M0 bits are counted as dummy clocks.

7.2

Write Enable (06h)

Write Enable instruction is for setting the Write Enable Latch (WEL) bit in the Status Register. The WEL bit must be set prior to

every Program, Erase and Write Status Register instruction. To enter the Write Enable instruction, CS goes low prior to the

instruction (06h) being driven onto the SI pin on the rising edge of SCK, and then driving CS high.

Figure 7-1.

Write Enable Instruction for SPI Mode (left) and QPI Mode (right)

7.3

Write Enable for Volatile Status Register (50h)

This i n s t r u c t i o n gives more flexibility to change the system configuration and memory protection schemes quickly

without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile

bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status Register (50h)

instruction must be issued prior to a Write Status Register (01h) instruction.

The Write Enable for Volatile Status Register instruction (Figure 7-2) does not set the Write Enable Latch (WEL) bit.

Once Write Enable for Volatile Status Register is set, a Write Enable instruction should not have been issued prior to

setting Write Status Register instruction (01h or 31h). When the Write Enable for Volatile Status Register (50h) is

executed in QPI Mode, the SUS bit (S15) and Reserved bits (S13, S12, S11 and S10) of the Status Register-2 must be

driven to high after Write Status Register instruction (01h). Once the Read Status Register (05h or 31h) instruction is

issued, the read values of the SUS bit (S15) and Reserved bits (S13, S12, S11 and S10) of the Status Register-2 are

ignored.

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