M69KB096AB datasheet(30/73 Pages) STMICROELECTRONICS

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7 Configuration Registers

M69KB096AB

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7.3.5

WAIT Configuration Bit (BCR8)

The system memory microcontroller uses the WAIT signal to control data transfer during

Synchronous Burst Read and Write operations.

The WAIT Configuration bit is used to determine when the transition of the WAIT output signal

between the asserted and the de-asserted state occurs with respect to valid data available on

the data bus.

When the Wait Configuration bit is set to ‘0’, data is valid or invalid on the first Clock rising edge

immediately after the WAIT signal transition to the de-asserted or asserted state.

When the Wait Configuration bit is set to ‘1’ (default settings), the WAIT signal transition occurs

one clock cycle prior to the data bus going valid or invalid.

See Figure 9: WAIT Configuration Example for an example of WAIT configuration.

7.3.6

Driver Strength Bits (BCR5-BCR4)

The Driver Strength bits allow to set the output drive strength to adjust to different data bus

loading. Normal driver strength (full drive) and reduced driver strength (half drive and a quarter

drive) are available.

By default, outputs are configured at ‘half drive” strength.

7.3.7

Burst Wrap Bit (BCR3)

Burst Read operations can be confined inside the 4, 8, 16 or 32 Word boundary (wrap mode). If

the wrap mode is not enabled, the device outputs data sequentially up to the end of the row,

regardless of burst boundaries.

The Burst Wrap bit is used to select between ‘wrap’ and ‘no wrap’ mode.

7.3.8

Burst Length Bits (BCR2-BCR0)

The Burst Length bits set the number of Words to be output or input during a Synchronous

Burst Read or Write operation. They can be set for 4 Words, 8 Words, 16 Words, 32 Words or

Continuous Burst (default settings), where all the Words are output or input sequentially

regardless of address boundaries (see also Table 10: Burst Type Definition).

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