M69KB096AB datasheet(14/73 Pages) STMICROELECTRONICS

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4 Low-power modes

M69KB096AB

14/73

4.3

Partial Array Self Refresh

The Partial Array Self Refresh (PASR) performs a limited refresh of part of the PSRAM array.

This mechanism enables the device to reduce the Standby current by refreshing only the part of

the memory array that contains essential data. Different refresh options can be defined by

setting the RCR0 to RCR2 bits of the RCR:

●

Full array

●

One eighth of the array

●

One half of the array

●

One quarter of the array

●

None of the array.

These memory areas can be located either at the top or bottom of the memory array.

The WAIT signal is used for arbitration when a read/write operation is launched while an on-

chip refresh is in progress. If locations are addressed while they are undergoing refresh, the

WAIT signal will be asserted for additional clock cycles, until the refresh has completed (see

Figure 6: Refresh Collision during Synchronous Burst Read in Variable Latency Mode). When

the refresh operation is completed, the read or write operation will be allowed to continue

normally.

4.4

Automatic Temperature Compensated Self Refresh

The leakage current of DRAM capacitive storage elements increases with the temperature. At

lower temperatures, the refresh rate can be decreased to minimize the Standby current.

The M69KB096AB is based on DRAM architecture, consequently it requires increasingly

frequent refresh operations to maintain data integrity as the temperature increases. The

Automatic Temperature Compensated Self Refresh mechanism (TCSR) that the devices

feature, automatically adjusts the refresh rate depending on the operating temperature.

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