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M69KB096AB bảng dữ liệu(PDF) 26 Page - STMicroelectronics |
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M69KB096AB bảng dữ liệu(HTML) 26 Page - STMicroelectronics |
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26 / 73 page ![]() 7 Configuration Registers M69KB096AB 26/73 7 Configuration Registers The M69KB096AB features three registers: ● The Bus Configuration Register (BCR) ● The Refresh Configuration Register (RCR) ● The Device ID Register (DIDR). BCR and RCR are user-programmable registers that define the device operating mode. They are automatically loaded with default settings during Power-Up, and selected by address bits A18 and A19 (see Table 8: Register Selection). DIDR is a read-only register that contains information about the device identification. It is selected by setting address bit A18 to ‘1’ with A19 ‘don’t care’. The configuration registers (only BCR and RCR) can be programmed and read using two methods: ● The CR Controlled Method (or Hardware Method) ● The Software Method. 7.1 Programming and Reading Registers using the CR Controlled Method 7.1.1 Read Configuration Register The content of a register is read by issuing a read operation with Configuration Register Enable signal, CR, High, VIH. Address bits A18 and A19 select the register to be read (see Table 8: Register Selection). The value contained in the register is then available on data bits DQ0 to DQ15. The BCR, RCR and DIDR can be read either in normal asynchronous or synchronous mode. The CR pin has to be driven high prior to any access. See Tables 6 and 7 for a detailed description of Configuration register Read by the CR Controlled methods and Figures 17 and 28, CR Controlled Configuration Register Read waveforms in asynchronous and synchronous mode. 7.1.2 Program Configuration Register BCR and RCR registers can be programmed by issuing a bus write operation, in asynchronous or synchronous mode (NOR-Flash or Full Synchronous), with Configuration Register Enable signal, CR, High, VIH. Address bits A18 and A19 allow to select between BCR and RCR (see Table 8: Register Selection). In synchronous mode, the values placed on address lines A0 to A15 are latched on the rising edge of L, E, or W, whichever occurs first. In asynchronous mode, a register is programmed by toggling L signal. LB and UB are ‘don’t care’. The CR pin has to be driven high prior to any access. |
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