M69KB096AB datasheet(20/73 Pages) STMICROELECTRONICS

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6 Synchronous Operating modes

M69KB096AB

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6.3.2

Fixed Latency

The latency programmed in the BCR is the real latency. The number of clock cycles is

calculated by taking into account the time necessary for a refresh operation and the time

necessary for an initial Burst access. This limits the operating frequency for a given latency

value (see Table 4: Operating Frequency versus Latency and Figure 4: Latency Configuration

(Fixed Latency Mode)).

It is recommended to use the Fixed Latency mode if the microcontroller cannot monitor the

WAIT signal.

6.3.3

Row Boundary Crossing

The M69KB096AB features 128-Word rows. Row boundary crossings between adjacent rows

may occur during Burst Read and Write operations. Row boundary crossings are not handled

automatically by the PSRAM.

The microcontroller must stop the Burst operation at the row boundary and restart it at the

beginning of the next row. Burst operations must be stopped by driving the Chip Enable signal,

E, High, after the WAIT signal falling edge. E must transition:

●

before the third Clock cycle after the WAIT signal goes Low if BCR[8] = 0,

●

before the fourth Clock cycle after WAIT signal goes Low if BCR[8] = 1.

Refer to Figure 26 and Figure 30 for details on how to manage row boundary crossings during

burst operations.

6.4

Synchronous Burst Read Interrupt

Ongoing Burst Read operations can be interrupted to start a new Burst cycle by either of the

following means:

●

Driving E High, VIH, and then Low, VIL on the next clock cycle (recommended). If

necessary, refresh cycles will be added during the new Burst operation to schedule any

outstanding refresh. If Variable Latency mode is set, additional wait cycles will be added if

a refresh operation is scheduled during the Synchronous Burst Read Interrupt. WAIT

monitoring is mandatory for proper system operation.

●

Starting a new Synchronous Burst Read operation without toggling E.

An ongoing Burst Read operation can be interrupted only after the first valid data is output.

When a new Burst access starts, I/O signals immediately become high impedance.

6.5

Synchronous Burst Write Interrupt

Ongoing Burst Write operations can be interrupted to start a new Burst cycle by either of the

following means:

●

Driving E High, VIH, and then Low, VIL on the next clock cycle (recommended),

●

Starting a new Synchronous Burst Write without toggling E. Considering that Burst Writes

are always performed in Fixed Latency mode, refresh is never scheduled. A maximum

Chip Enable, E, low time (tELEH) must be respected for proper device operation.

An ongoing Burst Write can be interrupted only after the first data is input. When a new Burst

access starts, I/O signals immediately become high impedance.

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