68HC705JB4 datasheet(13/134 Pages) FREESCALE

13 / 134 page

February 24, 1999

GENERAL RELEASE SPECIFICATION

MC68HC05JB4

GENERAL DESCRIPTION

MOTOROLA

REV 2

1-1

SECTION 1

GENERAL DESCRIPTION

The MC68HC05JB4 is a member of the low-cost, high-performance M68HC05

Family of 8-bit microcontroller units (MCUs). The M68HC05 Family is based on

the customer-speciﬁed integrated circuit (CSIC) design strategy. All MCUs in the

family use the popular M68HC05 central processing unit (CPU) and are available

with a variety of subsystems, memory sizes and types, and package types.

The MC68HC05JB4 is speciﬁcally designed to be used in applications where a

low speed (1.5Mbps) Universal Serial Bus (USB) interface is required.

1.1

FEATURES

•

Industry standard M68HC05 CPU core

•

Memory-mapped input/output (I/O) registers

•

3584 Bytes of user ROM

•

176 Bytes of user RAM (includes 64 byte stack)

•

19 Bidirectional I/O pins with the following added features:

– PA[0:7]:

Software enable Internal pull-up resistor (50k

Ω typical)

– PA[0:3]:

Built-in schmitt triggered input level

–

Maskable as extra input sources for IRQ interrupt

–

Maskable Negative-Edge Only or Negative-Edge

–

and Low-Level Interrupt Capability

– PA4:

IRQ2 with built-in schmitt triggered input

– PA[5:7]:

10mA Sink output drive

– PA[6:7]:

Maskable 10mA/25mA sink output drive

–

Software enable Slow Edge Pull Down Devices

– PB[0:4]:

Software enable Internal pull-up resistor (50k

Ω typical)

–

Software enable Slow Edge Pull Down Devices

– PB[0]:

ICAP1 with built-in schmitt triggered input

– PB[3:4]:

AD[4:5]

– PC[0:3]:

AD[0:3]

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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