68HC705JB4 datasheet(86/134 Pages) FREESCALE

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GENERAL RELEASE SPECIFICATION

February 24, 1999

MOTOROLA

UNIVERSAL SERIAL BUS MODULE

MC68HC05JB4

10-20

REV 2

SUSPND — USB Suspend Flag

To save power, this read/write bit should be set by the software if a 3ms con-

stant idle state is detected on USB bus. Setting this bit stops the clock to the

USB and causes the USB module to enter Suspend mode. Unnecessary ana-

log circuitry will be powered down. Software must clear this bit after the

Resume ﬂag (RESUMF) is set while this Resume interrupt ﬂag is serviced.

TXD0IE — Endpoint 0 Transmit Interrupt Enable

This read/write bit enables the Transmit Endpoint 0 to generate a USB interrupt

when the TXD0F bit becomes set.

1 =

USB interrupts enabled for Transmit Endpoint 0

0 =

USB interrupts disabled for Transmit Endpoint 0

RXD0IE — Endpoint 0 Receive Interrupt Enable

This read/write bit enables the Transmit Endpoint 0 to generate a USB interrupt

when the RXD0F bit becomes set.

1 =

USB interrupts enabled for Receive Endpoint 0

0 =

USB interrupts disabled for Receive Endpoint 0

TXD0FR — Endpoint 0 Transmit Flag Reset

Writing a logic 1 to this write only bit will clear the TXD0F bit if it is set.Writing a

logic 0 to TXD0FR has no effect. Reset clears this bit.

RXD0FR — Endpoint 0 Receive Flag Reset

Writing a logic 1 to this write only bit will clear the RXD0F bit if it is set.Writing a

logic 0 to RXD0FR has no effect. Reset clears this bit.

10.5.3 USB Interrupt Register 1 (UIR1)

TXD1F — Endpoint 1/Endpoint 2 Data Transmit Flag

This read only bit is shared by Endpoint 1 and Endpoint 2. It is set after the data

stored in the shared Endpoint 1/Endpoint 2 transmit buffer has been sent and

an ACK handshake packet from the host is received. Once the next set of data

is ready in the transmit buffers, software must clear this ﬂag by writing a logic 1

to the TXD1FR bit. To enable the next data packet transmission, TX1E must

also be set. If TXD1F bit is not cleared, a NAK handshake will be returned in

the next IN transaction.

Reset clears this bit. Writing a logic 0 to TXD1F has no effect.

1 =

Transmit on Endpoint 1 or Endpoint 2 has occurred

0 =

Transmit on Endpoint 1 or Endpoint 2 has not occurred

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

UIR1

TXD1F

EOPF

RESUMF

TXD1IE

EOPIE

$003A

RESUMFR

TXD1FR

EOPFR

reset:

00000000

= Unimplemented

Figure 10-22. USB Interrupt Register 1(UIR1)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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