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68HC705JB4 bảng dữ liệu(PDF) 55 Page - Freescale Semiconductor, Inc |
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68HC705JB4 bảng dữ liệu(HTML) 55 Page - Freescale Semiconductor, Inc |
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55 / 134 page ![]() February 24, 1999 GENERAL RELEASE SPECIFICATION MC68HC05JB4 MULTI-FUNCTION TIMER MOTOROLA REV 2 8-3 8.3 MFT REGISTERS 8.3.1 Timer Counter Register (TCNT) $09 The Timer Counter Register is a read-only register which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked at fOP÷4 and can be used for various functions including a software input capture. Extended time periods can be attained using the TOF function to incre- ment a temporary RAM storage location thereby simulating a 16-bit (or more) counter. The value of each bit of the TCNT is shown in Figure 8-2. This register is cleared by reset. Figure 8-2. Timer Counter Register 8.3.2 Timer Control/Status Register (TCSR) $08 The TCSR contains the timer interrupt flag bits, the timer interrupt enable bits, and the real time interrupt rate select bits. Bit 2 and bit 3 are write-only bits which will read as logical zeros. Figure 8-3 shows the value of each bit in the TCSR follow- ing reset. Figure 8-3. Timer Control/Status Register (TCSR) TOF - Timer Overflow Flag The TOF is a read-only flag bit. 1 = Set when the 8-bit ripple counter rolls over from $FF to $00. A TIMER Interrupt request will be generated if TOFE is also set. 0 = Reset by writing a logical one to the TOF acknowledge bit, TOFR. Writing to the TOF flag bit has no effect on its value. This bit is cleared by reset. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TCNT R TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0 $0009 W reset: 00000000 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TCSR R TOF RTIF TOFE RTIE 00 RT1 RT0 $0008 W TOFR RTIFR reset: 00000011 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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