ATMEGA640 datasheet(339/436 Pages) MICROCHIP

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339

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

30.8.1

Serial Programming Pin Mapping

Figure 30-10. Serial Programming and Verify(1)

Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin.

2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8V - 5.5V.When programming the

EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and

there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every

memory location in both the Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock

(SCK) input are defined as follows:

Low: > 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck >= 12MHz

High: > 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck >= 12MHz

30.8.2

Serial Programming Algorithm

When writing serial data to the ATmega640/1280/1281/2560/2561, data is clocked on the rising edge of SCK.

When reading data from the ATmega640/1280/1281/2560/2561, data is clocked on the falling edge of SCK. See

Figure 30-12 on page 342 for timing details.

To program and verify the ATmega640/1280/1281/2560/2561 in the serial programming mode, the following

sequence is recommended (see four byte instruction formats in Table 30-17 on page 340):

1. Power-up sequence:

Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the program-

mer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive

pulse of at least two CPU clock cycles duration after SCK has been set to “0”.

2. Wait for at least 20ms and enable serial programming by sending the Programming Enable serial instruc-

tion to pin PDI.

Table 30-15. Pin Mapping Serial Programming

Symbol

Pins (TQFP-100)

Pins (TQFP-64)

I/O

Description

PDI

PB2

PE0

Serial Data in

PDO

PB3

PE1

Serial Data out

SCK

PB1

Serial Clock

VCC

GND

XT AL1

SCK

PDO

PDI

RESET

+1.8V - 5.5V

AVCC

+1.8V - 5.5V

(2)

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