ATMEGA640 datasheet(23/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

8.3.1

EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space, see “Register Description” on page 34.

The write access time for the EEPROM is given in Table 8-1. A self-timing function, however, lets the user software

detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some pre-

cautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on power-up/down. This

causes the device for some period of time to run at a voltage lower than specified as minimum for the clock fre-

quency used. See “Preventing EEPROM Corruption” on page 25. for details on how to avoid problems in these

situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. See the description

of the EEPROM Control Register for details on this; “Register Description” on page 34.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When

the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

The calibrated Oscillator is used to time the EEPROM accesses. Table 8-1 lists the typical programming time for

EEPROM access from the CPU.

The following code examples show one assembly and one C function for writing to the EEPROM. The examples

assume that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will occur

during execution of these functions. The examples also assume that no Flash Boot Loader is present in the soft-

ware. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.

Table 8-1.

EEPROM Programming Time

Symbol

Number of Calibrated RC Oscillator Cycles

Typ Programming Time

EEPROM write (from CPU)

26,368

3.3ms

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