ATMEGA640 datasheet(50/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

11. Power Management and Sleep Modes

Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR

provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements.

11.1 Sleep Modes

Figure 10-1 on page 39 presents the different clock systems in the ATmega640/1280/1281/2560/2561, and their

distribution. The figure is helpful in selecting an appropriate sleep mode. Table 11-1 shows the different sleep

modes and their wake-up sources.

Note:

1. Only recommended with external crystal or resonator selected as clock source.

2. If Timer/Counter2 is running in asynchronous mode.

3. For INT7:4, only level interrupt.

To enter any of the sleep modes, the SE bit in “SMCR – Sleep Mode Control Register” on page 54 must be written

to logic one and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select

which sleep mode will be activated by the SLEEP instruction. See Table 11-2 on page 54 for a summary.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for

four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruc-

tion following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from

sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.

11.2 Idle Mode

When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU

but allowing the SPI, USART, Analog Comparator, ADC, 2-wire Serial Interface, Timer/Counters, Watchdog, and

the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the

other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer

Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not

required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control

and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conver-

sion starts automatically when this mode is entered.

Table 11-1.

Active Clock Domains and Wake-up Sources in the Different Sleep Modes.

Active Clock Domains

Oscillators

Wake-up Sources

Sleep Mode

Idle

X(2)

ADCNRM

X(2)

X(3)

XX(2)

Power-down

X(3)

Power-save

X(2)

X(3)

Standby(1)

XX(3)

Extended Standby

X(2)

XX(2)

X(3)

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