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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ATMEGA640 bảng dữ liệu(PDF) 338 Page - Microchip Technology |
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ATMEGA640 bảng dữ liệu(HTML) 338 Page - Microchip Technology |
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338 / 436 page  338 ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands. 2. tWLRH_CE is valid for the Chip Erase command. 30.8 Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using a serial programming bus while RESET is pulled to GND. The serial programming interface consists of pins SCK, PDI (input) and PDO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 30-15 on page 339, the pin mapping for serial programming is listed. Not all packages use the SPI pins dedicated for the internal Serial Peripheral Interface - SPI. Table 30-14. Parallel Programming Characteristics, VCC = 5V ±10% Symbol Parameter Min Typ Max Units VPP Programming Enable Voltage 11.5 12.5 V IPP Programming Enable Current 250 A tDVXH Data and Control Valid before XTAL1 High 67 ns tXLXH XTAL1 Low to XTAL1 High 200 tXHXL XTAL1 Pulse Width High 150 tXLDX Data and Control Hold after XTAL1 Low 67 tXLWL XTAL1 Low to WR Low 0 tXLPH XTAL1 Low to PAGEL high 0 tPLXH PAGEL low to XTAL1 high 150 tBVPH BS1 Valid before PAGEL High 67 tPHPL PAGEL Pulse Width High 150 tPLBX BS1 Hold after PAGEL Low 67 tWLBX BS2/1 Hold after WR Low 67 tPLWL PAGEL Low to WR Low 67 tBVWL BS2/1 Valid to WR Low 67 tWLWH WR Pulse Width Low 150 tWLRL WR Low to RDY/BSY Low 0 1 s tWLRH WR Low to RDY/BSY High(1) 3.7 4.5 ms tWLRH_CE WR Low to RDY/BSY High for Chip Erase(2) 7.5 9 tXLOL XTAL1 Low to OE Low 0 ns tBVDV BS1 Valid to DATA valid 0 250 tOLDV OE Low to DATA Valid 250 tOHDZ OE High to DATA Tri-stated 250 |
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