ATMEGA640 datasheet(343/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

while still allowing In-System Programming via the JTAG interface. Note that this technique can not be used when

using the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be dedicated for

this purpose.

During programming the clock frequency of the TCK Input must be less than the maximum frequency of the chip.

The System Clock Prescaler can not be used to divide the TCK Clock Input into a sufficiently low frequency.

As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers.

30.9.1

Programming Specific JTAG Instructions

The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions useful for program-

ming are listed below.

The OPCODE for each instruction is shown behind the instruction name in hex format. The text describes which

Data Register is selected as path between TDI and TDO for each instruction.

The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be used as an idle

state between JTAG sequences. The state machine sequence for changing the instruction word is shown in Figure

30-13.

Figure 30-13. State Machine Sequence for Changing the Instruction Word

Test-Logic-Reset

Run-Test/Idle

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Select-IR Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

Select-DR Scan

Capture-DR

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