MPF5024AMBA0ES datasheet(78/93 Pages) NXP

78 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

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Product data sheet

Rev. 1 — 15 April 2020

78 / 93

17.3 Default hardwire configuration

If VDDOTP = V1P5D, the device loads the configuration from the default hardwire

configuration directly into the corresponding I2C functional registers each time the

registers need to be reloaded.

When using the hardwire configuration, the TRIM values are still loaded from the OTP

fuses. In the event of a TRIM loading failure, the corresponding fault flag is set to 1.

When the hardwire configuration is used, the PF5024 does not allow TBB mode

operation. When TBBEN = V1P5D, the device enters a debug mode. In this mode of

operation, the device ignores the default value of the LPM_OFF bit and moves into the

QPU_Off state, regardless of the result of the self-test. However, the actual result of the

self-test is notified by the STEST_NOK flag.

• When the self-test is successful, the STEST_NOK flag is set to 0

• When the self-test has failed, the STEST_NOK flag is set to 1

During hardwire configuration, the OTP_NOK flag is always set to 0.

When any of the TRIM_NOK, OTP_NOK or STEST_NOK flags are set, any PWRUP

event is ignored until the flags are cleared by writing a 0. These flags can only be written

when the system is in the debug mode, (TBBEN = V1P5D). In normal operation, the

TRIM_NOK, OTP_NOK and STEST_NOK flags are read only.

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