MPF5024AMBA0ES datasheet(7/93 Pages) NXP

7 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

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Product data sheet

Rev. 1 — 15 April 2020

7 / 93

– SW1 to SW4: 0.4 V to 1.8 V; 2500 mA; 2 % accuracy

– Dynamic voltage scaling

– Configurable as a multiphase regulator

– VTT termination mode on SW2

– Programmable current limit

– Spread-spectrum and manual tuning of switching frequency

• PGOOD output and monitor

– Global PGOOD output and PGOOD monitor

– Independent PGOOD output for each regulator

• Independent enable input for each regulator

• Clock synchronization through configurable input/output sync pin

• System features

– Fast PMIC startup

– Advanced state machine for seamless processor interface

– High speed I2C interface support (up to 3.4 MHz)

– User programmable Standby and Off modes

– Programmable soft start sequence and power down sequence

– Programmable regulator configuration

• OTP (One-time programmable) memory for device configuration

• Monitoring circuit to fit ASIL B safety level

– Independent voltage monitoring with programmable fault protection

– Advance thermal monitoring and protection

– External watchdog monitoring and programmable internal watchdog counter

– I2C CRC and write protection mechanism

– Analog built-in self-test (ABIST)

12.2 Functional block diagram

aaa-030043

PF5024

FUNCTIONAL BLOCK DIAGRAM

CLOCK MANAGEMENT

EXTERNAL CLOCK SYNC

SPREAD SPECTRUM

MANUAL FREQUENCY TUNING

LOGIC AND CONTROL

I2C

WATCHDOG

MCU INTERFACE

REGULATOR CONTROL

FAULT DETECTION

FUNCTIONAL SAFETY

FAULT DETECTION AND

PROTECTION

(THERMAL/UV/OV/ILIM)

OTP

(FLEXIBLE CONFIGURATION)

SW1 (SINGLE/MULTI)

(0.4 V TO 1.8 V, 2.5 A)

SW2 (SINGLE/MULTI)

(VTT/0.4 V TO 1.8 V, 2.5 A)

SW3 (SINGLE/MULTI)

(0.4 V TO 1.8 V, 2.5 A)

SW4 (SINGLE/MULTI)

(0.4 V TO 1.8 V, 2.5 A)

Figure 4. Functional block diagram

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