MPF5024AMBA0ES datasheet(27/93 Pages) NXP

27 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 15 April 2020

27 / 93

aaa-030050

Power Down

Sequence

Power Down

Delay

Regulator

Outputs

RESETBMCU

PWRON

Shutdown

Event

OFF State

System On

State

Power Down

Sequence

Power Down Delay

Figure 11. Power down delay

The default value of the OTP_PD_SEQ_DLY[1:0] bits on an unprogrammed OTP device

shall be 00.

14.7 Fault detection

Three types of faults are monitored per regulator: UV, OV and ILIM. Faults are monitored

during power up sequence, run, standby and WD reset states. A fault event is notified to

the MCU through the INTB pin if the corresponding fault is not masked.

The fault configuration registers are reset to their default value after the power up

sequences, and system must configure them as required during the boot-up process via

I2C commands.

For each type of fault, there is an I2C bit that is used to select whether the regulator is

kept enabled or disabled when the corresponding regulator experience a fault event.

SWx_ILIM_STATE

• 0 = regulator disables upon an ILIM fault event

• 1 = regulator remains on upon an ILIM fault event

SWx_OV_STATE

• 0 = regulator disables upon an OV fault event

• 1 = regulator remains on upon an OV fault event

SWx_UV_STATE

• 0 = regulator disables upon an UV fault event

• 1 = regulator remains on upon an UV fault event

The following table lists the functional bits associated with enabling/disabling the external

regulators when they experience a fault.

Table 23. Regulator control during fault event bits

Regulator

Bit to disable the

regulator during current

limit

Bit to disable the

regulator during

undervoltage

Bit to disable the

regulator during

overvoltage

SWx

SWx_ILIM_STATE

SWx_UV_STATE

SWx_OV_STATE

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