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MPF5024AMBA0ES bảng dữ liệu(PDF) 36 Page - NXP Semiconductors |
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MPF5024AMBA0ES bảng dữ liệu(HTML) 36 Page - NXP Semiconductors |
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36 / 93 page  NXP Semiconductors PF5024 Power management integrated circuit (PMIC) for high performance applications PF5024 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1 — 15 April 2020 36 / 93 Register name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 SW UV MASK — — — — SW4_UV_M SW3_UV_M SW2_UV_M SW1_UV_M SW UV SENSE — — — — SW4_UV_S SW3_UV_S SW2_UV_S SW1_UV_S SW OV INT — — — — SW4_OV_I SW3_OV_I SW2_OV_I SW1_OV_I SW OV MASK — — — — SW4_OV_M SW3_OV_M SW2_OV_M SW1_OV_M SW OV SENSE — — — — SW4_OV_S SW3_OV_S SW2_OV_S SW1_OV_S PWRON INT BGMON_I PWRON_8S_I PWRON_4S_I PRON_3S_I PWRON_2S_I PWRON_1S_I PWRON_REL_I PWRON_PUSH_I PWRON MASK BGMON_M PWRON_8S_M PWRON_4S_M PRON_3S_M PWRON_2S_M PWRON_1S_M PWRON_REL_M PWRON_PUSH_M PWRON SENSE BGMON_S — — — — — — PWRON_S EN_SENSE — — — — EN4_S EN3_S EN2_S EN1_S SYS INT EWARN_I PWRON_I OV_I UV_I ILIM_I MODE_I STATUS2_I STATUS1_I 14.9 I/O interface pins The PF5024 PMIC is fully programmable via the I2C interface. Additional communication between MCU, PF5024 and other companion PMIC is provided by direct logic interfacing including INTB, RESETBMCU, PGOOD, among other pins. aaa-030054 PF5024 MCU PMIC1 PF5024 PMIC2 V1P5A Figure 17. I/O interface diagram Table 27. I/O electrical specifications Symbol Parameter Min Typ Max Unit PWRON_VIL PWRON low input voltage — — 0.4 V PWRON_VIH PWRON high input voltage 1.4 — 5.5 V STANDBY_VIL STANDBY low input voltage — — 0.4 V STANDBY_VIH STANDBY high input voltage 1.4 — 5.5 V RESETBMCU_VOL RESETBMCU low output voltage −2.0 mA load current 0 — 0.4 V |
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